Investigation of Process-Induced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETs

Abstract

we propose a process and device design strategy for L-g = 14 nm Si bulk n/p-FinFETs based on the effects of process-induced geometry variability on device performance. A calibrated TCAD simulation was used to design and optimize structures and these were also tested under various process split conditions. By comparing the I-V data from process-changed devices with nominal CMOS, relationships between process- induced geometry variation and device performance were investigated and analyzed. Moreover a DC/RF compact model was executed to observe the geometry variability effects on ring oscillator and RF applications. Finally key circuit design factors to mitigate process variability are suggested. (C) 2014 Elsevier Ltd. All rights reserved.