Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior

Abstract

The spatial position and energy level of the effective oxide trap in SiC DMOSFET were investigated using Trap Spectroscopy by Charge Injection and Sensing (TSCIS) method. It was found that the oxygen vacancy traps at 1.7 eV above from the valence band of SiO2 make threshold voltage (V-th) shift under high negative gate bias stress condition. To further understanding the extracted oxide trap, the repetitive negative stress and recovery test at V-G = +/- 40 V were executed. The results confirm that Vth and subthreshold swing (SS) change were caused by the process induced pre-existed hole traps instead of the stress induced trap generation. This hole trapping also reduced the Stress Induced Leakage Current (SILC) after the negative bias stress.