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Low Design Overhead Timing Error Correction Scheme for Elastic Clock Methodology

International Symposium on Low Power Electronics and Design (ISLPED), 2017-07-24

Conference
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors

International Symposium on Low Power Electronics and Design (ISLPED), page. 303 - 308, 2011-08-01

Conference
Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

International Symposium on Low Power Electronics and Design (ISLPED), 2018-07-23

Conference
Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

International Symposium on Low Power Electronics and Design (ISLPED), 2018-07-23

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