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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 백록현 | - |
| dc.contributor.author | 강창용 | - |
| dc.contributor.author | 김태우 | - |
| dc.contributor.author | 고동휘 | - |
| dc.contributor.author | 김대현 | - |
| dc.contributor.author | T.Michalak | - |
| dc.contributor.author | C.Borst | - |
| dc.contributor.author | D.Veksler | - |
| dc.contributor.author | G.Bersuker | - |
| dc.contributor.author | R.Hill | - |
| dc.contributor.author | C.Hobbs | - |
| dc.contributor.author | P.D.Kirsch | - |
| dc.date.accessioned | 2018-05-24T11:24:11Z | - |
| dc.date.available | 2018-05-24T11:24:11Z | - |
| dc.date.created | 2017-02-23 | - |
| dc.date.issued | 2013-12-09 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/49469 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE International Electron Devices Meeting | - |
| dc.relation.isPartOf | ELECTRON DEVICES MEETING (IEDM), 2013 IEEE INTERNATIONAL | - |
| dc.title | Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE International Electron Devices Meeting | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.title | IEEE International Electron Devices Meeting | - |
| dc.contributor.affiliatedAuthor | 백록현 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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- 백록현BAEK, ROCK HYUN
- Dept of Electrical Enginrg