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dc.contributor.author백록현-
dc.contributor.author강창용-
dc.contributor.author손창우-
dc.contributor.authorC.Hobbs-
dc.contributor.authorP.Kirsch-
dc.contributor.authorR.Jammy-
dc.date.accessioned2018-05-24T11:24:19Z-
dc.date.available2018-05-24T11:24:19Z-
dc.date.created2017-02-23-
dc.date.issued2013-06-10-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/49472-
dc.publisherIEEE-
dc.relation.isPartOfInternational Symposium on VLSI Technology (VLSI2013)-
dc.relation.isPartOfINTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY DIGEST-
dc.titleEffects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitationInternational Symposium on VLSI Technology (VLSI2013)-
dc.citation.conferencePlaceUS-
dc.citation.titleInternational Symposium on VLSI Technology (VLSI2013)-
dc.contributor.affiliatedAuthor백록현-
dc.description.journalClass1-
dc.description.journalClass1-

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백록현BAEK, ROCK HYUN
Dept of Electrical Enginrg
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