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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 백록현 | - |
| dc.contributor.author | 손창우 | - |
| dc.contributor.author | 강창용 | - |
| dc.contributor.author | 고명동 | - |
| dc.contributor.author | 박찬훈 | - |
| dc.contributor.author | 김성호 | - |
| dc.contributor.author | 정의영 | - |
| dc.contributor.author | 이정수 | - |
| dc.contributor.author | P.Kirsch | - |
| dc.contributor.author | R.Jammy | - |
| dc.contributor.author | J.C.Lee | - |
| dc.contributor.author | 정윤하 | - |
| dc.date.accessioned | 2018-05-24T11:24:22Z | - |
| dc.date.available | 2018-05-24T11:24:22Z | - |
| dc.date.created | 2017-02-23 | - |
| dc.date.issued | 2013-04-22 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/49473 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE VLSI-TSA (2013) | - |
| dc.relation.isPartOf | INTERNATIONAL SYMPOSIUM ON VLSI-TSA | - |
| dc.title | Effects of fin height of tapered FinFETs on the sub-22nm System on Chip (SoC) application using TCAD simulation | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE VLSI-TSA (2013) | - |
| dc.citation.conferencePlace | CH | - |
| dc.citation.title | IEEE VLSI-TSA (2013) | - |
| dc.contributor.affiliatedAuthor | 백록현 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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- 백록현BAEK, ROCK HYUN
- Dept of Electrical Enginrg