3.8 mW 10 Gbit/s CDR for intra-panel interface with a modulated training pattern
SCIE
SCOPUS
- Title
- 3.8 mW 10 Gbit/s CDR for intra-panel interface with a modulated training pattern
- Authors
- Lee, D.; Kim, J. -J.
- Date Issued
- 2017-08
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Abstract
- A modulated training pattern for intra-panel interface is proposed and is applied to design power-efficient clock and data recovery (CDR) circuits for intra-panel interface. By modulating the position of the rising edge of the training pattern, the number of the delay cells to generate the multi-phase clock to capture display data safely is reduced. As a result, power, area, and electro-magnetic interference characteristics can be improved over the conventional training pattern. A phaselocked loop-based CDR circuit with the proposed scheme in a 65 nm CMOS technology is designed. The measured lock range was between 6 and 10 Gbit/s and the power efficiency was 0.38 mW/Gbit/s at 10 Gbit/s inputs.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/50570
- DOI
- 10.1049/el.2017.1726
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 53, no. 16, page. 1098 - 1099, 2017-08
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- There are no files associated with this item.
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