DC Field | Value | Language |
---|---|---|
dc.contributor.author | Moon, Kibong | - |
dc.contributor.author | Kwak, Myounghoon | - |
dc.contributor.author | Park, Jaesung | - |
dc.contributor.author | Lee, Dongwook | - |
dc.contributor.author | Hwang, Hyunsang | - |
dc.date.accessioned | 2018-06-15T05:33:13Z | - |
dc.date.available | 2018-06-15T05:33:13Z | - |
dc.date.created | 2017-09-14 | - |
dc.date.issued | 2017-08 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/50595 | - |
dc.description.abstract | We report on a 1-transisor/2-resistor (1T2R) synapse device with improved conductance linearity and conductance ratio under an identical pulse condition for hardware neural networks with high pattern-recognition accuracy. Utilizing an additional series-connected resistor, the conductance linearity of a synapse device was significantly improved owing to the reduced initial voltage drop on an resistive RAM (RRAM) device during depression conditions. Moreover, to maximize the conductance ratio of a synapse device, we utilized a steep subthreshold region of an MOSFET by a parallel connection of an RRAM and a transistor. A small change in voltage on the RRAM directly controlled the gate bias of the MOSFET, which causes a large change in the drain current. Compared with a conventional RRAM synapse device, the 1T2R synapse device shows an improved conductance linearity and conductance ratio (>x100). Finally, we confirmed an excellent classification accuracy by using a neural network simulation based on a multilayer perceptron. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.subject | Analog memory | - |
dc.subject | linearity | - |
dc.subject | neuromorphic | - |
dc.subject | PCMO | - |
dc.subject | RRAM | - |
dc.subject | resistive switching | - |
dc.subject | synapse device | - |
dc.title | Improved Conductance Linearity and Conductance Ratio of 1T2R Synapse Device for Neuromorphic Systems | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2017.2721638 | - |
dc.type.rims | ART | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.38, no.8, pp.1023 - 1026 | - |
dc.identifier.wosid | 000406429600006 | - |
dc.date.tcdate | 2019-02-01 | - |
dc.citation.endPage | 1026 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 1023 | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 38 | - |
dc.contributor.affiliatedAuthor | Moon, Kibong | - |
dc.contributor.affiliatedAuthor | Kwak, Myounghoon | - |
dc.contributor.affiliatedAuthor | Park, Jaesung | - |
dc.contributor.affiliatedAuthor | Lee, Dongwook | - |
dc.contributor.affiliatedAuthor | Hwang, Hyunsang | - |
dc.identifier.scopusid | 2-s2.0-85023758394 | - |
dc.description.journalClass | 1 | - |
dc.description.journalClass | 1 | - |
dc.description.wostc | 8 | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordAuthor | Analog memory | - |
dc.subject.keywordAuthor | linearity | - |
dc.subject.keywordAuthor | neuromorphic | - |
dc.subject.keywordAuthor | PCMO | - |
dc.subject.keywordAuthor | RRAM | - |
dc.subject.keywordAuthor | resistive switching | - |
dc.subject.keywordAuthor | synapse device | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
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