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Cited 51 time in webofscience Cited 54 time in scopus
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dc.contributor.authorMoon, Kibong-
dc.contributor.authorKwak, Myounghoon-
dc.contributor.authorPark, Jaesung-
dc.contributor.authorLee, Dongwook-
dc.contributor.authorHwang, Hyunsang-
dc.date.accessioned2018-06-15T05:33:13Z-
dc.date.available2018-06-15T05:33:13Z-
dc.date.created2017-09-14-
dc.date.issued2017-08-
dc.identifier.issn0741-3106-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/50595-
dc.description.abstractWe report on a 1-transisor/2-resistor (1T2R) synapse device with improved conductance linearity and conductance ratio under an identical pulse condition for hardware neural networks with high pattern-recognition accuracy. Utilizing an additional series-connected resistor, the conductance linearity of a synapse device was significantly improved owing to the reduced initial voltage drop on an resistive RAM (RRAM) device during depression conditions. Moreover, to maximize the conductance ratio of a synapse device, we utilized a steep subthreshold region of an MOSFET by a parallel connection of an RRAM and a transistor. A small change in voltage on the RRAM directly controlled the gate bias of the MOSFET, which causes a large change in the drain current. Compared with a conventional RRAM synapse device, the 1T2R synapse device shows an improved conductance linearity and conductance ratio (>x100). Finally, we confirmed an excellent classification accuracy by using a neural network simulation based on a multilayer perceptron.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.relation.isPartOfIEEE ELECTRON DEVICE LETTERS-
dc.subjectAnalog memory-
dc.subjectlinearity-
dc.subjectneuromorphic-
dc.subjectPCMO-
dc.subjectRRAM-
dc.subjectresistive switching-
dc.subjectsynapse device-
dc.titleImproved Conductance Linearity and Conductance Ratio of 1T2R Synapse Device for Neuromorphic Systems-
dc.typeArticle-
dc.identifier.doi10.1109/LED.2017.2721638-
dc.type.rimsART-
dc.identifier.bibliographicCitationIEEE ELECTRON DEVICE LETTERS, v.38, no.8, pp.1023 - 1026-
dc.identifier.wosid000406429600006-
dc.date.tcdate2019-02-01-
dc.citation.endPage1026-
dc.citation.number8-
dc.citation.startPage1023-
dc.citation.titleIEEE ELECTRON DEVICE LETTERS-
dc.citation.volume38-
dc.contributor.affiliatedAuthorMoon, Kibong-
dc.contributor.affiliatedAuthorKwak, Myounghoon-
dc.contributor.affiliatedAuthorPark, Jaesung-
dc.contributor.affiliatedAuthorLee, Dongwook-
dc.contributor.affiliatedAuthorHwang, Hyunsang-
dc.identifier.scopusid2-s2.0-85023758394-
dc.description.journalClass1-
dc.description.journalClass1-
dc.description.wostc8-
dc.type.docTypeArticle-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordAuthorAnalog memory-
dc.subject.keywordAuthorlinearity-
dc.subject.keywordAuthorneuromorphic-
dc.subject.keywordAuthorPCMO-
dc.subject.keywordAuthorRRAM-
dc.subject.keywordAuthorresistive switching-
dc.subject.keywordAuthorsynapse device-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-

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