Conference
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design
- Title
- Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI Design
- Date Issued
- 2010-08-04
- Publisher
- Asqed
- Article Type
- Conference
- Citation
- Asia Symposium on Quality Electronic Design(Asqed) 2010, page. 314 - 317, 2010-08-04
- Files in This Item:
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
Communities & Collection
Related Researcher
- 김영환KIM, YOUNG HWAN
- Dept of Electrical Enginrg