DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kang, Yesung | - |
dc.contributor.author | Kim, Jaewoo | - |
dc.contributor.author | Kim, Sunmin | - |
dc.contributor.author | Shin, Sunhae | - |
dc.contributor.author | Jang, E-San | - |
dc.contributor.author | Jeong, Jae Won | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.contributor.author | KANG, SEOKHYEONG | - |
dc.date.accessioned | 2019-04-08T08:57:56Z | - |
dc.date.available | 2019-04-08T08:57:56Z | - |
dc.date.created | 2019-03-12 | - |
dc.date.issued | 2017-05-23 | - |
dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/98483 | - |
dc.description.abstract | Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs. We design a novel ternary multiplier based on a ternary CMOS (T-CMOS) compact model. To estimate performance and energy efficiency of our ternary design, we construct a standard ternary-cell library and exploit a ternary static timing analysis (T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design. | - |
dc.publisher | IEEE | - |
dc.relation.isPartOf | Proc. IEEE International Symposium on Multiple-Valued Logic | - |
dc.relation.isPartOf | Proc. IEEE International Symposium on Multiple-Valued Logic | - |
dc.title | A Novel Ternary Multiplier based on Ternary CMOS Compact Model | - |
dc.type | Conference | - |
dc.type.rims | CONF | - |
dc.identifier.bibliographicCitation | Proc. IEEE International Symposium on Multiple-Valued Logic | - |
dc.citation.conferenceDate | 2017-05-22 | - |
dc.citation.conferencePlace | JA | - |
dc.citation.title | Proc. IEEE International Symposium on Multiple-Valued Logic | - |
dc.contributor.affiliatedAuthor | KANG, SEOKHYEONG | - |
dc.description.journalClass | 2 | - |
dc.description.journalClass | 2 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
library@postech.ac.kr Tel: 054-279-2548
Copyrights © by 2017 Pohang University of Science ad Technology All right reserved.