A Novel Ternary Multiplier based on Ternary CMOS Compact Model
- Title
- A Novel Ternary Multiplier based on Ternary CMOS Compact Model
- Authors
- Kang, Yesung; Kim, Jaewoo; Kim, Sunmin; Shin, Sunhae; Jang, E-San; Jeong, Jae Won; Kim, Kyung Rok; KANG, SEOKHYEONG
- Date Issued
- 2017-05-23
- Publisher
- IEEE
- Abstract
- Multiple-valued logic (MVL) has potential advantages for energy-efficient design by reducing a circuit complexity. Because of physical device and circuit realization issues, however, there are relatively small number of researches on MVL circuit designs. We design a novel ternary multiplier based on a ternary CMOS (T-CMOS) compact model. To estimate performance and energy efficiency of our ternary design, we construct a standard ternary-cell library and exploit a ternary static timing analysis (T-STA). The proposed ternary multiplier design achieves significant total power reduction and performance improvement over conventional ternary design.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/98483
- Article Type
- Conference
- Citation
- Proc. IEEE International Symposium on Multiple-Valued Logic, 2017-05-23
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- There are no files associated with this item.
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