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Showing results 1 to 6 of 6
Thesis
A Delay Locked Loop with a Feedback Edge Combiner of Duty Cycle Corrector and A TIA with negative input-resistance for on-chip interconnect

Thesis(Doctor), 2019

Conference
A Wide Range Delay Locked Loop for DDR4

한국반도체학술대회, 2017-02-15

Conference
A Wide Range Delay Locked Loop for DDR4

반도체학술대회 2016, 2016-02-13

Conference
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

2014년 SoC 학술대회, 2014-05-17

Conference
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

2014 SoC 학술대회, 2014-05-17

Conference
USB 2.0 high-speed PHY interface를 위한 전송선의 Verilog modeling

대한전자공학회 SoC 학술대회, 2014-05-17

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