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Browsing by  AuthorKAM, DONG YUN

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Showing results 1 to 8 of 8
Conference
A 1.1µs 1.56Gb/s/mm^2 cost-efficient large-list SCL polar decoder using fully-reusable LLR buffers in 28nm CMOS technology

2022 IEEE VLSI Symposium on Technology and Circuits, 2022-06-16

Conference
Complexity-latency tradeoff for 5G SCL polar decoder architecture

제 29회 한국반도체학술대회, 2022-01-26

Conference
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks

2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021, 2021-11-08

Conference
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023-02-26

Conference
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023-02-26

Conference
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks

2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023-02-26

Article
Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithmSCIESCOPUS

IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, page. 1774 - 1787, 2022-04

Conference
Ultra-low-latency LPDC decoding architecture using reweighted offset min-sum algorithm

IEEE International Symposium on Circuits and Systems (ISCAS), 2020-10-15

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