Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

Abstract

Process (systematic) variations of sub-5-nm node fin field-effect transistors (FinFETs) and nanosheet field-effect transistors (NSFETs) were investigated thoroughly using fully calibrated TCAD. All the process parameters consisting of front-end-as well as middle-of-line structure were independently randomized within feasible process conditions. A novel process scheme called source/drain patterning (SDP), having a superior performance by decreasing outer fringing capacitance through the downsized source/drain (S/D) epi, has also been analyzed for the variability study. SDP FinFETs have smaller variations of threshold voltages (V-th), OFF-state currents (I-OFF), and effective currents (I-eff) than conventional ones because the subfin leakage is effectively controlled by bottom oxide (BO) beneath the source/drain instead of high punchthrough-stopper doping. The Spearman's correlation results between process parameters, I-OFF, and I-eff, showed that the process parameters affecting the short-channel effects vary I-OFF and I-eff greatly. Especially, the most critical one was the fin width (W-fin) for FinFETs. SDP NSFETs have the smallest variations of V-th, I-OFF, and I-eff. The BO blocks the bottom leakage completely, and the variations of nanosheet (NS) thickness(T-NS) aremuchsmaller than those of W-fin due to the different process flows: epitaxial growth for T-NS versus patterning for W-fin. Therefore, NSFETs are promising to reduce the variations of V-th, I-OFF, and I-eff in the sub-5-nm node.