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Browsing "Department of Electrical Engineering (전자전기공학과)" by  Title

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Showing results 481 to 510 of 11,052
Thesis
A Delay Locked Loop with a Feedback Edge Combiner of Duty Cycle Corrector and A TIA with negative input-resistance for on-chip interconnect

Thesis(Doctor), 2019

Article
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, vol. 63, no. 2, page. 141 - 145, 2016-02

Conference
A delay-dependent robust stability criterion for uncertain time-delay systems

Preceeding of 1998 American Control Conference, page. 1963 - 1965, 1998-07-01

Article
A delay-dependent stability criterion for systems with uncertain time-invariant delaysSCIESCOPUS

IEEE TRANSACTIONS ON AUTOMATIC CONTROL, vol. 44, no. 4, page. 876 - 877, 1999-04

Article
A Delta Sigma-Digitized polar RF transmitterSCIESCOPUS

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 55, no. 12, page. 2679 - 2690, 2007-12

Thesis
A Delta-Sigma ADC for Column-Parallel Mutual-Capacitive Touch Sensor

Thesis(Master), 2015

Conference
A Delta-Sigma-Digitized RF transmitter

MTT-S Int. Microw. Symp. Dig, page. 81 - 84

Article
A Depletion-mode InP MOSFET with a Liquid Phase Oxidized InGaAs GateSCIE

COMPOUND SEMICONDUCTORS 2001, no. 170, page. 125 - 129, 2002-01

Conference
A Depletion-mode InP MOSFET with a Liquid Phase Oxidized InGaAs Gate

International Symposium on Compound Semiconductors 2001, 2001-10

Conference
A derivation of the excess mean square error for affine projection algorithms using the condition number

ICCAS 2007, page. 1708 - 1711, 2007-10-18

Conference
A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

International SoC Design Conference, 2008-11-24

Conference
A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

International SoC Design Conference (ISOCC), 2008-11-24

Conference
A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

International SoC Design Conference

Article
A Design Guide of 3-stage CMOS Operational Amplifier with Nested Gm-C Frequency CompensationKCI

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 7, no. 1, page. 20 - 27, 2007-03

Article
A design guide of 3-stage CMOS operational amplifier with nested Gm-C frequency compensationKCI

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 7, no. 1, page. 20 - 27, 2007-01

Conference
A Design of Neural Network-Based Equalizer for Nonlinear Satellite Communication Channels

2022 3rd Korea Artificial Intelligence Conference, 2022-09-28

Conference
A design of optimal overlay system

IEEE International Conference on Communications 2005, page. 433 - 437, 2005-05-16

Conference
A design of optimal overlay system inducing zero interference to legacy systems

IEEE GLOBECOM 2007, 2007-11-26

Conference
A Design on a 10bit-50MS/s Pipelined CMOS ADC using an Error Correction Scheme

CAD 및 VLSI 설계연구회 학술발표회, 2001-05-01

Thesis
A DFE Adaptation for Human Body Communication

Thesis(Master), 2019

Article
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory InterfacesSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 68, no. 6, page. 1862 - 1866, 2021-06

Conference
A Diffusion LMS Algorithm Robust to Impulsive Noises

ICS 2017, 2017-04-21

Conference
A Diffusion Strategy for the Multichannel Active Noise Control

The 2016 International Conference on Computational Science and Computational Intelligence (CSCI), 2016-12-15

Article
A diffusion subband adaptive filtering algorithm for distributed estimation using variable step size and new combination method based on the MSDSCIESCOPUS

Digital Signal Processing, vol. 48, page. 361 - 369, 2016-01

Article
A digital CMOS PWCL with fixed-delay rising edge and digital stability controlSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 53, no. 10, page. 1063 - 1067, 2006-10

Article
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch CalibrationSCIESCOPUS

IEICE TRANSACTIONS ON ELECTRONICS, vol. E93C, no. 1, page. 132 - 135, 2010-01

Conference
A Digital PWCL for Multi-Phase Clock Applications

International SoC Design Conference, page. 239 - 242, 2005-10-01

Article
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog CircuitsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 60, no. 11, page. 2845 - 2856, 2013-11

Article
A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADCSCIESCOPUS

Journal of Circuits, Systems and Computers (JSTS), vol. 25, no. 12, 2016-12

Article
A DIRECT DIGITAL-CONTROL FOR THE PHASE-CONTROLLED RECTIFIERSCIESCOPUS

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, vol. 38, no. 5, page. 337 - 343, 1991-10

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