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Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node
- Title
- Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node
- Authors
- 백록현; 강창용; 김태우; 고동휘; 김대현; T.Michalak; C.Borst; D.Veksler; G.Bersuker; R.Hill; C.Hobbs; P.D.Kirsch
- Date Issued
- 2013-12-09
- Publisher
- IEEE
- Article Type
- Conference
- Citation
- IEEE International Electron Devices Meeting, 2013-12-09
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Related Researcher
- 백록현BAEK, ROCK HYUN
- Dept of Electrical Enginrg