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Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node

Title
Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node
Authors
백록현강창용김태우고동휘김대현T.MichalakC.BorstD.VekslerG.BersukerR.HillC.HobbsP.D.Kirsch
Date Issued
2013-12-09
Publisher
IEEE
URI
https://oasis.postech.ac.kr/handle/2014.oak/49469
Article Type
Conference
Citation
IEEE International Electron Devices Meeting, 2013-12-09
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백록현BAEK, ROCK HYUN
Dept of Electrical Enginrg
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