Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs

Abstract

In this paper, we systematically evaluate dc/ac performances of sub-7-nm node fin field-effect transistors (FinFETs) and nanosheet FETs (NSEETs) using fully calibrated 3-D TCAD. The stress effects of all the devices were carefully considered in terms of carrier mobility and velocity averaged within the active regions. For detailed AC analysis, the parasitic capacitances were extracted and decomposed into several components using TCAD RF simulation platform. FinFETs improved the gate electrostatics by decreasing fin widths to 5 nm, but the fin heights were unable to improve RC delay due to the trade-off between on-state currents and gate capacitances. The NSEETs have better on-state currents than do the FinFETs because of larger effective widths (W-eff) under the same device area. Particularly p-type NSEETs have larger compressive stress within the active regions affected by metal gate encircling all around the channels, thus improving carrier mobility and velocity much. On the other hand, the NSEETs have larger gate capacitances because larger W-eff increase the gate-to-source/drain overlap and outer-fringing capacitances. In spite of that, sub-7-nm node NSEETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.