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KIM, JAE JOON(김재준)

Department: Dept. Convergence IT Engineering(IT융합공학과)

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Publication & Time Cited Count (For the Last 5 years)

Results 1-20 of 38 (Search time: 0.001 seconds).

Conference

Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks

3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021, 2021-06

Conference

Unifying Activation- and Timing-based Learning Rules for Spiking Neural Networks

Conference on Neural Information Processing Systems (Neurips), 2020-12-10

Conference

Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization

39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020, 2020-11-03

Conference

Time-step interleaved weight reuse for LSTM neural network computing

2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020, 2020-08-11

Conference

Algorithm/Hardware Co-design for in-memory neural network computing with minimal peripheral circuit overhead

57th ACM/IEEE Design Automation Conference, DAC 2020, 2020-07-22

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BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations

International Conference on Learning Representations, 2020-04-28

Conference

A Novel In-DRAM Accelerator Architecture for Binary Neural Network

23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020, 2020-04-16

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A 44.1 TOPS/W Precision-Scalable Hardware Accelerator for Quantized Neural Networks in 28nm CMOS

Custom Integrated Circuits Conference, 2020-03-23

Conference

Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping

Asian Solid-State Circuits Conference, 2019-11-05

Conference

Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array

Symposium on VLSI Circuits, 2019-06-12

Conference

BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation

Design automation conference, 2019-06-04

Conference

Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns

Design automation conference, 2019-06-04

Conference

Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network

International Conference on Learning Representations, 2019-05-08

Conference

Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors

Custom Integrated Circuits Conference, 2019-04-17

Conference

Effect of Device Variation on mapping Binary Neural Network to Memristor Crossbar Array

Design Automation and Test in Europe, 2019-03-29

Conference

In-Memory Batch-Normalization for Resistive Memory based Binary Neural Network Hardware

Asian South-Pacific Design Automation Conference, 2019-01-23

Conference

Input-splitting of large neural networks for power-efficient accelerator with resistive crossbar memory array

23rd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2018, 2018-07-24

Conference

Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

International Symposium on Low Power Electronics and Design (ISLPED), 2018-07-23

Conference

Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay

International Symposium on Low Power Electronics and Design (ISLPED), 2018-07-23

Conference

Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio

International Conference on Learning Representations, 2018-05-02

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