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Conference

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), page. 37 - 42, 2019-05-21

Conference

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019, page. 37 - 42, 2019-05-21

Conference

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020, page. 155 - 158, 2020-11

Conference

Fast Chip-Package-PCB Coanalysis Methodology for Power Integrity of Multi-domain High-Speed Memory: A Case Study

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018-03-22

Conference

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization

Proc. ACM/IEEE Design Automation Conference, 2017-06-20

Conference

Fence-Region-Aware Mixed-Height Standard Cell Legalization

Great Lakes Symposium on VLSI, 2019-05-10

Conference

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks

2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023, 2023-04-17

Conference

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks

2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023, 2023-04-17

Conference

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks

2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023, 2023-04-17

Conference

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks

2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023, 2023-04-17

Conference

GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN

32nd Great Lakes Symposium on VLSI, GLSVLSI 2022, page. 177 - 181, 2022-06-06

Conference

Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM

18th International System-on-Chip Design Conference, ISOCC 2021, page. 109 - 110, 2021-10-08

Conference

GRASP based Metaheuristics for Layout Pattern Classification

International Conference on Computer-Aided Design, 2017-11-15

Conference

GRLC: Grid-based run-length compression for energy-efficient CNN accelerator

2020 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020, 2020-08

Conference

Late breaking results: Reinforcement learning-based power management policy for mobile device systems

57th ACM/IEEE Design Automation Conference, DAC 2020, 2020-07

Conference

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

17th International System-on-Chip Design Conference, ISOCC 2020, page. 254 - 255, 2020-10

Conference

MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors

2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023, 2023-04-17

Conference

Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator

2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021, page. 1809 - 1814, 2021-02-02

Conference

Machine Learning-based Fast Circuit Simulation for Analog Circuit Array

5th ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2023, 2023-09-10

Conference

MCQA: Multi-constraint qubit allocation for near-FTQC device

41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, 2022-10-30

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