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Showing results 1 to 11 of 11
Conference
Accurate Extraction of Volume Trap Density from Si-Nanowire FET using the Newly Developed Cylindrical Coordinate Based 1/f noise model

17th Korean Conference on Semiconductors (2010), 2010-02-24

Conference
Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer

Solid State Devices and Materials (SSDM2011), 2011-09-28

Conference
Analysis of Parasitic Bottom Capacitance in n- and p-type Si-Nanowire Field Effect Transistors on Bulk

IEEE-NANO (2011), 2011-08-15

Conference
C-V Characteristics and Analysis of Undoped Gate-All-Around Nanowire FET Array

Solid State Devices and Materials (SSDM2010), page. 1277 - 1278, 2010-09-21

Conference
Characteristics of Gate-All-Around Si-NWFET, including Rsd, Cylindrical Coordinate Based 1/f Noise and Hot Carrier Effects

IEEE IRPS(2010), 2010-05-02

Conference
Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration

, 2012-08

Conference
Comparative Study of C-V Characteristics in Si-NWFET and MOSFET (Invited paper)

IEEE Nanotechnology Materials and Devices Conference (NMDC2010), 2010-10-12

Conference
GIDL analysis of underlap double gate MOSFET with variable channel thickness and doping using quantum simulation

대한전자공학회 하계학술대회 2010, 2010-06-16

Conference
Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy

IEEE SISPAD 2012, 2012-09-05

Conference
Reliable Extraction of Series Resistance in Silicon Nanowire FETs Using Y-function Technique

IEEE Nanotechnology Materials and Devices Conference (NMDC2011), 2011-10-19

Conference
Series Resistance Behavior Extracted from Silicon Nanowire Transistors Using the Y-function Technique

Solid State Devices and Materials (SSDM2009), page. 1108 - 1109, 2009-10-06

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